arm-sdk

os build toolkit for various embedded devices
git clone https://git.parazyd.org/arm-sdk
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commit 81e0db08c4b935bbe2fc37f4bb1c4c4446fe446c
parent bb8d9fb830dfdf53cc805828da788db634b88bbd
Author: parazyd <parazyd@dyne.org>
Date:   Sun,  1 May 2016 23:24:09 +0200

extra files for chromeveyron

Diffstat:
Aarm/extra/bins/brcm_patchram_plus | 0
Aarm/extra/brcm/BCM4354_003.001.012.0306.0659.hcd | 0
Aarm/extra/brcm/BCM4354_003.001.012.0322.0679.hcd | 0
Aarm/extra/brcm/brcmfmac4354-sdio.bin | 0
Aarm/extra/brcm/brcmfmac4354-sdio.txt | 155+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Aarm/extra/elan_i2c.bin | 0
Aarm/extra/elants_i2c_0000.bin | 0
Aarm/extra/elants_i2c_0a91.bin | 0
Aarm/extra/maxtouch-ts.cfg | 57+++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Aarm/extra/maxtouch-ts.fw | 0
Aarm/extra/patches/0001-UPSTREAM-soc-rockchip-add-handler-for-usb-uart-funct.patch | 306+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Aarm/extra/patches/0002-fix-brcmfmac-oops-and-race-condition.patch | 95+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
12 files changed, 613 insertions(+), 0 deletions(-)

diff --git a/arm/extra/bins/brcm_patchram_plus b/arm/extra/bins/brcm_patchram_plus Binary files differ. diff --git a/arm/extra/brcm/BCM4354_003.001.012.0306.0659.hcd b/arm/extra/brcm/BCM4354_003.001.012.0306.0659.hcd Binary files differ. diff --git a/arm/extra/brcm/BCM4354_003.001.012.0322.0679.hcd b/arm/extra/brcm/BCM4354_003.001.012.0322.0679.hcd Binary files differ. diff --git a/arm/extra/brcm/brcmfmac4354-sdio.bin b/arm/extra/brcm/brcmfmac4354-sdio.bin Binary files differ. diff --git a/arm/extra/brcm/brcmfmac4354-sdio.txt b/arm/extra/brcm/brcmfmac4354-sdio.txt @@ -0,0 +1,155 @@ +# Sample variables file for BCM94354Z NGFF 22x30mm iPA, iLNA board with PCIe/SDIO for production package +# SDIO interface +NVRAMRev=$Rev: 373428 $ +sromrev=11 +boardrev=0x1224 +boardtype=0x0707 +boardflags=0x02400201 +#enable LNA1 bypass for both 2G & 5G + +#boardflags2=0xc0800000 +boardflags2=0x00802000 + +boardflags3=0x4800000a +#boardnum=57410 +macaddr=00:11:22:33:44:55 +ccode=0 +regrev=0 +antswitch=0 +pdgain5g=4 +pdgain2g=4 +tworangetssi2g=0 +tworangetssi5g=0 +paprdis=0 +femctrl=10 +vendid=0x14e4 +devid=0x43a3 +manfid=0x2d0 +#prodid=0x052e +nocrc=1 +otpimagesize=502 +xtalfreq=37400 +rxgains2gelnagaina0=0 + +#rxgains2gtrisoa0=3 +rxgains2gtrisoa0=7 + +rxgains2gtrelnabypa0=0 +rxgains5gelnagaina0=0 + +#rxgains5gtrisoa0=4 +rxgains5gtrisoa0=11 + +rxgains5gtrelnabypa0=0 +rxgains5gmelnagaina0=0 + +#rxgains5gmtrisoa0=4 +rxgains5gmtrisoa0=13 + +rxgains5gmtrelnabypa0=0 +rxgains5ghelnagaina0=0 + +#rxgains5ghtrisoa0=4 +rxgains5ghtrisoa0=12 + +rxgains5ghtrelnabypa0=0 +rxgains2gelnagaina1=0 + +#rxgains2gtrisoa1=3 +rxgains2gtrisoa1=7 + +rxgains2gtrelnabypa1=0 +rxgains5gelnagaina1=0 + +#rxgains5gtrisoa1=4 +rxgains5gtrisoa1=10 + +rxgains5gtrelnabypa1=0 +rxgains5gmelnagaina1=0 + +#rxgains5gmtrisoa1=4 +rxgains5gmtrisoa1=11 + +rxgains5gmtrelnabypa1=0 +rxgains5ghelnagaina1=0 + +#rxgains5ghtrisoa1=4 +rxgains5ghtrisoa1=11 + +rxgains5ghtrelnabypa1=0 +rxchain=3 +txchain=3 +aa2g=3 +aa5g=3 +agbg0=2 +agbg1=2 +aga0=2 +aga1=2 +tssipos2g=1 +extpagain2g=2 +tssipos5g=1 +extpagain5g=2 +tempthresh=255 +tempoffset=255 +rawtempsense=0x1ff +pa2ga0=-147,5992,-705 +pa2ga1=-161,5991,-701 +pa5ga0=-194,5999,-739,-188,6057,-743,-185,6001,-725,-171,5978,-715 +pa5ga1=-190,6103,-757,-190,6105,-759,-190,6105,-757,-184,6111,-746 +subband5gver=0x4 +pdoffsetcckma0=0x4 +pdoffsetcckma1=0x4 +pdoffset40ma0=0x0000 +pdoffset80ma0=0x0000 +pdoffset40ma1=0x0000 +pdoffset80ma1=0x0000 +maxp2ga0=70 +maxp5ga0=58,58,58,58 +maxp2ga1=70 +maxp5ga1=58,58,58,58 +cckbw202gpo=0x1111 +cckbw20ul2gpo=0x0000 +mcsbw202gpo=0x66666666 +mcsbw402gpo=0xAAAAAAAA +dot11agofdmhrbw202gpo=0x4444 +ofdmlrbw202gpo=0x0044 +mcsbw205glpo=0x66666666 +mcsbw405glpo=0x66666666 +mcsbw805glpo=0xAAAAAAAA +mcsbw205gmpo=0x66666666 +mcsbw405gmpo=0x66666666 +mcsbw805gmpo=0xAAAAAAAA +mcsbw205ghpo=0x66666666 +mcsbw405ghpo=0x66666666 +mcsbw805ghpo=0xAAAAAAAA +mcslr5glpo=0x0000 +mcslr5gmpo=0x0000 +mcslr5ghpo=0x0000 +sb20in40hrpo=0x0 +sb20in80and160hr5glpo=0x0 +sb40and80hr5glpo=0x0 +sb20in80and160hr5gmpo=0x0 +sb40and80hr5gmpo=0x0 +sb20in80and160hr5ghpo=0x0 +sb40and80hr5ghpo=0x0 +sb20in40lrpo=0x0 +sb20in80and160lr5glpo=0x0 +sb40and80lr5glpo=0x0 +sb20in80and160lr5gmpo=0x0 +sb40and80lr5gmpo=0x0 +sb20in80and160lr5ghpo=0x0 +sb40and80lr5ghpo=0x0 +dot11agduphrpo=0x0 +dot11agduplrpo=0x0 +phycal_tempdelta=25 +temps_period=15 +temps_hysteresis=15 +AvVmid_c0=2,140,2,145,2,145,2,145,2,145 +AvVmid_c1=2,140,2,145,2,145,2,145,2,145 +AvVmid_c2=0,0,0,0,0,0,0,0,0,0 +rssicorrnorm_c0=4,4 +rssicorrnorm_c1=4,4 +rssicorrnorm5g_c0=1,2,3,1,2,3,6,6,8,6,6,8 +rssicorrnorm5g_c1=1,2,3,2,2,2,7,7,8,7,7,8 +ltecxmux=0x534201 +Ofdmfilttype=6 diff --git a/arm/extra/elan_i2c.bin b/arm/extra/elan_i2c.bin Binary files differ. diff --git a/arm/extra/elants_i2c_0000.bin b/arm/extra/elants_i2c_0000.bin Binary files differ. diff --git a/arm/extra/elants_i2c_0a91.bin b/arm/extra/elants_i2c_0a91.bin Binary files differ. diff --git a/arm/extra/maxtouch-ts.cfg b/arm/extra/maxtouch-ts.cfg @@ -0,0 +1,57 @@ +OBP_RAW V1 +A2 00 20 AB 20 34 21 +969531 +B5B0E5 +0044 0000 0049 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0026 0000 0040 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0047 0000 00A8 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0007 0000 0004 32 08 96 03 +0008 0000 000A 67 00 0A 0A 00 00 FF 01 00 00 +0009 0000 002F 83 00 00 1D 2E 00 82 28 03 01 0A 01 01 00 0A 05 08 00 1F 03 FF 04 03 03 01 01 00 00 00 00 0A 0C 32 32 02 00 43 E6 2D 5F 00 00 00 00 00 80 00 +0009 0001 002F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000F 0000 000B 00 00 00 00 00 00 00 00 00 00 00 +0012 0000 0002 00 00 +0013 0000 0006 00 00 00 00 00 00 +0018 0000 0013 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0018 0001 0013 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0019 0000 0015 03 00 C0 5D 20 4E 00 00 00 00 00 00 00 00 C8 00 00 00 00 00 00 +001B 0000 0007 00 00 00 00 00 00 00 +001B 0001 0007 00 00 00 00 00 00 00 +0028 0000 0005 00 00 00 00 00 +0028 0001 0005 00 00 00 00 00 +002A 0000 000D 21 19 1E 14 F0 00 00 00 00 00 00 03 00 +002A 0001 000D 00 00 00 00 00 00 00 00 00 00 00 00 00 +002B 0000 000C 00 00 00 00 00 00 00 00 00 00 00 00 +002E 0000 000B 00 00 18 18 00 00 00 00 00 00 0B +002F 0000 001C 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +002F 0001 001C 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0037 0000 0007 00 38 40 0A 01 00 C0 +0037 0001 0007 00 00 00 00 00 00 00 +0038 0000 0033 01 00 01 44 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0039 0000 0003 00 00 00 +0039 0001 0003 00 00 00 +003D 0000 0005 00 00 00 00 00 +003D 0001 0005 00 00 00 00 00 +003D 0002 0005 00 00 00 00 00 +003D 0003 0005 00 00 00 00 00 +003E 0000 004A 7D 03 00 10 00 03 00 05 2D 00 05 16 19 12 05 00 0A 05 01 72 0F 08 24 00 28 18 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +003F 0000 0019 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +003F 0001 0019 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0041 0000 0011 19 0F 00 00 00 00 00 00 00 00 08 00 00 00 00 00 00 +0042 0000 0003 00 00 00 +0046 0000 000A 00 00 00 00 00 00 00 00 00 00 +0046 0001 000A 00 00 00 00 00 00 00 00 00 00 +0046 0002 000A 00 00 00 00 00 00 00 00 00 00 +0046 0003 000A 00 00 00 00 00 00 00 00 00 00 +0046 0004 000A 00 00 00 00 00 00 00 00 00 00 +0046 0005 000A 00 00 00 00 00 00 00 00 00 00 +0046 0006 000A 00 00 00 00 00 00 00 00 00 00 +0046 0007 000A 00 00 00 00 00 00 00 00 00 00 +0046 0008 000A 00 00 00 00 00 00 00 00 00 00 +0046 0009 000A 00 00 00 00 00 00 00 00 00 00 +0046 000A 000A 00 00 00 00 00 00 00 00 00 00 +0046 000B 000A 00 00 00 00 00 00 00 00 00 00 +0049 0000 0006 00 00 00 00 00 00 +0049 0001 0006 00 00 00 00 00 00 +004D 0000 0004 00 00 00 00 +004F 0000 0003 00 00 00 diff --git a/arm/extra/maxtouch-ts.fw b/arm/extra/maxtouch-ts.fw Binary files differ. diff --git a/arm/extra/patches/0001-UPSTREAM-soc-rockchip-add-handler-for-usb-uart-funct.patch b/arm/extra/patches/0001-UPSTREAM-soc-rockchip-add-handler-for-usb-uart-funct.patch @@ -0,0 +1,306 @@ +From c0c863786b85a631e22eeae78f572d3f151af490 Mon Sep 17 00:00:00 2001 +From: Heiko Stuebner <heiko@sntech.de> +Date: Mon, 25 May 2015 16:38:07 +0200 +Subject: [PATCH 3/4] UPSTREAM: soc/rockchip: add handler for usb-uart + functionality + +Some Rockchip SoCs provide the possibility to use a usb-phy as passthru for +the debug uart, making it possible to get console output without needing to +open the device. + +This patch adds an early_initcall to enable this functionality conditionally +and also disables the corresponding usb controller in the devicetree. + +Change-Id: I397df8f402c752125cf512332398757b91a899f8 +Signed-off-by: Alexandru M Stan <amstan@chromium.org> +--- + drivers/soc/Kconfig | 1 + + drivers/soc/Makefile | 1 + + drivers/soc/rockchip/Kconfig | 13 ++ + drivers/soc/rockchip/Makefile | 1 + + drivers/soc/rockchip/rockchip_usb_uart.c | 223 +++++++++++++++++++++++++++++++ + 5 files changed, 239 insertions(+) + create mode 100644 drivers/soc/rockchip/Kconfig + create mode 100644 drivers/soc/rockchip/Makefile + create mode 100644 drivers/soc/rockchip/rockchip_usb_uart.c + +diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig +index 1ee0b57..ad2f71a 100644 +--- a/drivers/soc/Kconfig ++++ b/drivers/soc/Kconfig +@@ -2,6 +2,7 @@ menu "SOC (System On Chip) specific Drivers" + + source "drivers/soc/img/Kconfig" + source "drivers/soc/qcom/Kconfig" ++source "drivers/soc/rockchip/Kconfig" + source "drivers/soc/tegra/Kconfig" + + endmenu +diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile +index bc43b87..d80386c 100644 +--- a/drivers/soc/Makefile ++++ b/drivers/soc/Makefile +@@ -4,4 +4,5 @@ + + obj-$(CONFIG_SOC_IMG) += img/ + obj-$(CONFIG_ARCH_QCOM) += qcom/ ++obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ + obj-$(CONFIG_ARCH_TEGRA) += tegra/ +diff --git a/drivers/soc/rockchip/Kconfig b/drivers/soc/rockchip/Kconfig +new file mode 100644 +index 0000000..24d4e05 +--- /dev/null ++++ b/drivers/soc/rockchip/Kconfig +@@ -0,0 +1,13 @@ ++# ++# Rockchip Soc drivers ++# ++config ROCKCHIP_USB_UART ++ bool "Rockchip usb-uart override" ++ depends on ARCH_ROCKCHIP ++ select MFD_SYSCON ++ help ++ Say y here to enable usb-uart functionality. Newer Rockchip SoCs ++ provide means to repurpose one usb phy as uart2 output, making it ++ possible to get debug output without needing to open a device. ++ To enable this function on boot, add a rockchip.usb_uart option ++ to the kernel commandline. +diff --git a/drivers/soc/rockchip/Makefile b/drivers/soc/rockchip/Makefile +new file mode 100644 +index 0000000..b5dd6f8 +--- /dev/null ++++ b/drivers/soc/rockchip/Makefile +@@ -0,0 +1 @@ ++obj-$(CONFIG_ROCKCHIP_USB_UART) += rockchip_usb_uart.o +diff --git a/drivers/soc/rockchip/rockchip_usb_uart.c b/drivers/soc/rockchip/rockchip_usb_uart.c +new file mode 100644 +index 0000000..97754f9 +--- /dev/null ++++ b/drivers/soc/rockchip/rockchip_usb_uart.c +@@ -0,0 +1,223 @@ ++/* ++ * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/init.h> ++#include <linux/errno.h> ++#include <linux/mfd/syscon.h> ++#include <linux/of_address.h> ++#include <linux/of_platform.h> ++#include <linux/regmap.h> ++#include <linux/slab.h> ++ ++#define HIWORD_UPDATE(val, mask) \ ++ ((val) | (mask) << 16) ++ ++struct rockchip_uart_data { ++ const char *grf_compatible; ++ const char *usb_compatible; ++ phys_addr_t usb_phys_addr; ++ int (*init_uart)(const struct rockchip_uart_data *data, ++ struct regmap *grf); ++}; ++ ++static int enable_usb_uart = 0; ++ ++#define RK3288_UOC0_CON0 0x320 ++#define RK3288_UOC0_CON0_COMMON_ON_N BIT(0) ++#define RK3288_UOC0_CON0_DISABLE BIT(4) ++ ++#define RK3288_UOC0_CON2 0x328 ++#define RK3288_UOC0_CON2_SOFT_CON_SEL BIT(2) ++ ++#define RK3288_UOC0_CON3 0x32c ++#define RK3288_UOC0_CON3_UTMI_SUSPENDN BIT(0) ++#define RK3288_UOC0_CON3_UTMI_OPMODE_NODRIVING (1 << 1) ++#define RK3288_UOC0_CON3_UTMI_OPMODE_MASK (3 << 1) ++#define RK3288_UOC0_CON3_UTMI_XCVRSEELCT_FSTRANSC (1 << 3) ++#define RK3288_UOC0_CON3_UTMI_XCVRSEELCT_MASK (3 << 3) ++#define RK3288_UOC0_CON3_UTMI_TERMSEL_FULLSPEED BIT(5) ++#define RK3288_UOC0_CON3_BYPASSDMEN BIT(6) ++#define RK3288_UOC0_CON3_BYPASSSEL BIT(7) ++ ++/* ++ * Enable the bypass of uart2 data through the otg usb phy. ++ * Original description in the TRM. ++ * 1. Disable the OTG block by setting OTGDISABLE0 to 1’b1. ++ * 2. Disable the pull-up resistance on the D+ line by setting OPMODE0[1:0] to 2’b01. ++ * 3. To ensure that the XO, Bias, and PLL blocks are powered down in Suspend mode, set COMMONONN to 1’b1. ++ * 4. Place the USB PHY in Suspend mode by setting SUSPENDM0 to 1’b0. ++ * 5. Set BYPASSSEL0 to 1’b1. ++ * 6. To transmit data, controls BYPASSDMEN0, and BYPASSDMDATA0. ++ * To receive data, monitor FSVPLUS0. ++ * ++ * The actual code in the vendor kernel does some things differently. ++ */ ++static int __init rk3288_init_usb_uart(const struct rockchip_uart_data *data, ++ struct regmap *grf) ++{ ++ u32 val; ++ int ret; ++ ++ pr_info("%s\n", __func__); ++ ++ /* ++ * COMMON_ON and DISABLE settings are described in the TRM, ++ * but where not present in the original code. ++ */ ++ val = HIWORD_UPDATE(RK3288_UOC0_CON0_COMMON_ON_N ++ | RK3288_UOC0_CON0_DISABLE, ++ RK3288_UOC0_CON0_COMMON_ON_N ++ | RK3288_UOC0_CON0_DISABLE); ++ ret = regmap_write(grf, RK3288_UOC0_CON0, val); ++ if (ret) ++ return ret; ++ ++ // FIXME: this makes my system hang, for whatever reason ++ val = HIWORD_UPDATE(RK3288_UOC0_CON2_SOFT_CON_SEL, ++ RK3288_UOC0_CON2_SOFT_CON_SEL); ++ ret = regmap_write(grf, RK3288_UOC0_CON2, val); ++ if (ret) ++ return ret; ++ ++ val = HIWORD_UPDATE(RK3288_UOC0_CON3_UTMI_OPMODE_NODRIVING ++ | RK3288_UOC0_CON3_UTMI_XCVRSEELCT_FSTRANSC ++ | RK3288_UOC0_CON3_UTMI_TERMSEL_FULLSPEED, ++ RK3288_UOC0_CON3_UTMI_SUSPENDN ++ | RK3288_UOC0_CON3_UTMI_OPMODE_MASK ++ | RK3288_UOC0_CON3_UTMI_XCVRSEELCT_MASK ++ | RK3288_UOC0_CON3_UTMI_TERMSEL_FULLSPEED); ++ ret = regmap_write(grf, RK3288_UOC0_CON3, val); ++ if (ret) ++ return ret; ++ ++ val = HIWORD_UPDATE(RK3288_UOC0_CON3_BYPASSSEL ++ | RK3288_UOC0_CON3_BYPASSDMEN, ++ RK3288_UOC0_CON3_BYPASSSEL ++ | RK3288_UOC0_CON3_BYPASSDMEN); ++ ret = regmap_write(grf, RK3288_UOC0_CON3, val); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++const struct rockchip_uart_data rk3288_uart_data = { ++ .grf_compatible = "rockchip,rk3288-grf", ++ .usb_compatible = "rockchip,rk3288-usb", ++ .usb_phys_addr = 0xff580000, ++ .init_uart = rk3288_init_usb_uart, ++}; ++ ++static const struct of_device_id rockchip_usb_uart_ids[] = { ++ { .compatible = "rockchip,rk3288", .data = &rk3288_uart_data }, ++ { } ++}; ++ ++/* ++ * Find the usb controller using the shared usb-uart-phy in the dts and ++ * disable it. ++ */ ++static int __init ++rockchip_disable_usb_controller(const struct rockchip_uart_data *data) ++{ ++ struct device_node *np; ++ ++ for_each_compatible_node(np, NULL, data->usb_compatible) { ++ struct property *new_status; ++ struct resource res; ++ int ret; ++ ++ ret = of_address_to_resource(np, 0, &res); ++ if (ret) { ++ pr_err("%s: could not get address of usb controller %s\n", ++ __func__, np->full_name); ++ continue; ++ } ++ ++ /* not the controller we're looking for */ ++ if (res.start != data->usb_phys_addr) ++ continue; ++ ++ pr_info("%s: disabling usb controller %s\n", ++ __func__, np->full_name); ++ ++ new_status = kzalloc(sizeof(*new_status), GFP_KERNEL); ++ if (!new_status) ++ return -ENOMEM; ++ ++ new_status->name = kstrdup("status", GFP_KERNEL); ++ new_status->length = sizeof("disabled"); ++ new_status->value = kstrdup("disabled", GFP_KERNEL); ++ ++ return of_update_property(np, new_status); ++ } ++ ++ return 0; ++} ++ ++static const struct of_device_id *rockchip_usb_uart_data_lookup(void) ++{ ++ struct device_node *root; ++ const struct of_device_id *id; ++ ++ root = of_find_node_by_path("/"); ++ if (!root) ++ return NULL; ++ ++ id = of_match_node(rockchip_usb_uart_ids, root); ++ of_node_put(root); ++ ++ return id; ++} ++ ++static int __init rockchip_init_usb_uart(void) ++{ ++ const struct of_device_id *match; ++ const struct rockchip_uart_data *data; ++ struct regmap *grf; ++ int ret; ++ ++ if (!enable_usb_uart) ++ return 0; ++ ++ match = rockchip_usb_uart_data_lookup(); ++ if (!match) ++ return -ENOTSUPP; ++ ++ pr_info("%s: using settings for %s\n", __func__, match->compatible); ++ data = match->data; ++ ++ grf = syscon_regmap_lookup_by_compatible(data->grf_compatible); ++ if (IS_ERR(grf)) { ++ pr_err("%s: could not find GRF syscon\n", __func__); ++ return PTR_ERR(grf); ++ } ++ ++ ret = data->init_uart(data, grf); ++ if (ret) { ++ pr_err("%s: could not init usb_uart\n", __func__); ++ return ret; ++ } ++ ++ return rockchip_disable_usb_controller(data); ++} ++early_initcall(rockchip_init_usb_uart); ++ ++static int __init rockchip_usb_uart(char *buf) ++{ ++ enable_usb_uart = true; ++ return 0; ++} ++early_param("rockchip.usb_uart", rockchip_usb_uart); +-- +2.4.4 + diff --git a/arm/extra/patches/0002-fix-brcmfmac-oops-and-race-condition.patch b/arm/extra/patches/0002-fix-brcmfmac-oops-and-race-condition.patch @@ -0,0 +1,95 @@ +From 6dc781566c97f06b5c0d491f34c9b23e72cb74be Mon Sep 17 00:00:00 2001 +From: Kevin Mihelich <kevin@archlinuxarm.org> +Date: Thu, 2 Jul 2015 17:48:41 -0600 +Subject: [PATCH 4/4] fix brcmfmac oops and race condition + +This fixes a potential null pointer dereference by checking if null before +freeing the vif struct. + +Also works around a race condition between brcm_patchram_plus loading the BT +firmware, which exposes the wireless device, and the kernel loading bcrmfmac. +100ms delay loops up to 1s are added around the first three initialization +functions to hold off a failure until the device is actually ready. This is a +hack. + +Signed-off-by: Kevin Mihelich <kevin@archlinuxarm.org> +Edited by: parazyd <parazyd@dyne.org> + * Removed dhd_linux.c part of the patch since it is failing +--- + .../wireless-3.8/brcm80211/brcmfmac/dhd_common.c | 47 ++++++++++++++-------- + .../wireless-3.8/brcm80211/brcmfmac/dhd_linux.c | 4 +- + 2 files changed, 32 insertions(+), 19 deletions(-) + +diff --git a/drivers/net/wireless-3.8/brcm80211/brcmfmac/dhd_common.c b/drivers/net/wireless-3.8/brcm80211/brcmfmac/dhd_common.c +index 05d4042..7006d19 100644 +--- a/drivers/net/wireless-3.8/brcm80211/brcmfmac/dhd_common.c ++++ b/drivers/net/wireless-3.8/brcm80211/brcmfmac/dhd_common.c +@@ -252,25 +252,34 @@ int brcmf_c_preinit_dcmds(struct brcmf_if *ifp) + struct brcmf_join_pref_params join_pref_params[2]; + char *ptr; + s32 err; ++ int i; + + /* retreive mac address */ +- err = brcmf_fil_iovar_data_get(ifp, "cur_etheraddr", ifp->mac_addr, +- sizeof(ifp->mac_addr)); +- if (err < 0) { +- brcmf_err("Retreiving cur_etheraddr failed, %d\n", +- err); +- goto done; ++ for (i = 0; i < 9; i++) { ++ err = brcmf_fil_iovar_data_get(ifp, "cur_etheraddr", ifp->mac_addr, ++ sizeof(ifp->mac_addr)); ++ if (err < 0 && i == 9) { ++ brcmf_err("Retreiving cur_etheraddr failed, %d\n", ++ err); ++ goto done; ++ } else { ++ msleep(100); ++ } + } + memcpy(ifp->drvr->mac, ifp->mac_addr, sizeof(ifp->drvr->mac)); + + /* query for 'ver' to get version info from firmware */ +- memset(buf, 0, sizeof(buf)); +- strcpy(buf, "ver"); +- err = brcmf_fil_iovar_data_get(ifp, "ver", buf, sizeof(buf)); +- if (err < 0) { +- brcmf_err("Retreiving version information failed, %d\n", +- err); +- goto done; ++ for (i = 0; i < 10; i++) { ++ memset(buf, 0, sizeof(buf)); ++ strcpy(buf, "ver"); ++ err = brcmf_fil_iovar_data_get(ifp, "ver", buf, sizeof(buf)); ++ if (err < 0 && i == 9) { ++ brcmf_err("Retreiving version information failed, %d\n", ++ err); ++ goto done; ++ } else { ++ msleep(100); ++ } + } + ptr = (char *)buf; + strsep(&ptr, "\n"); +@@ -283,10 +292,14 @@ int brcmf_c_preinit_dcmds(struct brcmf_if *ifp) + strlcpy(ifp->drvr->fwver, ptr, sizeof(ifp->drvr->fwver)); + + /* set mpc */ +- err = brcmf_fil_iovar_int_set(ifp, "mpc", 1); +- if (err) { +- brcmf_err("failed setting mpc\n"); +- goto done; ++ for (i = 0; i < 10; i++) { ++ err = brcmf_fil_iovar_int_set(ifp, "mpc", 1); ++ if (err && i == 9) { ++ brcmf_err("failed setting mpc\n"); ++ goto done; ++ } else { ++ msleep(100); ++ } + } + + /* +2.4.4 +